Extended Kalman Filtering and Phase Detector Modeling for a Digital Phase-Locked Loop

The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering. Key–Words: Digital phase-locked loop (DPLL), phase detector, state estimation, extended Kalman filter (EKF)